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Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology which features very low on-state resistance. It is intended for use in automotive and general purpose switching applications.
BUK9505-30A
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V MAX. 30 75 230 175 5 4.6 UNIT V A W C m m
PINNING - TO220AB
PIN 1 2 3 tab gate drain DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
source drain
1 23
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS VGSM ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k tp50S Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 30 30 10 15 75 75 400 230 175 UNIT V V V V A A A W C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS in free air TYP. 60 MAX. 0.65 UNIT K/W K/W
August 1999
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
STATIC CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VDS = 30 V; VGS = 0 V; VGS = 10 V; VDS = 0 V VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 4.5 V; ID = 25 A Tj = 175C Tj = 175C MIN. 30 27 1 0.5 -
BUK9505-30A
TYP. 1.5 0.05 2 4.3 3.9 -
MAX. 2.0 2.3 10 500 100 5 9.3 4.6 5.4
UNIT V V V V V A A nA m m m m
DYNAMIC CHARACTERISTICS
Tmb = 25C unless otherwise specified SYMBOL Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. TYP. 6500 1500 1000 45 220 435 320 3.5 4.5 7.5 MAX. 8600 1800 1350 65 330 600 450 UNIT pF pF pF ns ns ns ns nH nH nH
VDD = 30 V; Rload =1.2; VGS = 5 V; RG = 10
Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 75 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 30 V TYP. 0.85 1.1 400 1.0 MAX. 75 240 1.2 UNIT A A V V ns C
August 1999
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 75 A; VDD 25 V; VGS = 5 V; RGS = 50 ; Tmb = 25 C MIN. -
BUK9505-30A
TYP. -
MAX. 500
UNIT mJ
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1000 ID/A RDS(ON) = VDS/ID 100 tp = 100uS 1mS 10mS 10 DC 100mS
0
20
40
60
80 100 Tmb / C
120
140
160
180
1
1
10
VDS/V
100
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
ID% Normalised Current Derating
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
120 110 100 90 80 70 60 50 40 30 20 10 0
1 D= 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0
Zth / (K/W)
P D
tp
D=
tp T t
T
0
20
40
60
80 100 Tmb / C
120
140
160
180
0.001
0.00001
0.001
t/S
0.1
10
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
August 1999
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
BUK9505-30A
10.0 7.0 ID/V 6.0 5.0 300
400
4.8 4.6 4.4
100
VGS/V = 4.2 4.0 3.8 3.6
ID/A 80
60 Tj/C = 40 175 25
200
3.4 3.2 3.0 2.8 2.6 2.4
100
20
0
0
0
2
4
VDS/V
6
8
10
0
0.5
1
1.5
VGS/V
2
2.5
3
3.5
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
RDS(ON)/mOhm
Fig.8. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
150 gfs/S
11 10 9
VGS/V = 8 7 6 5 4 3 0 3.0 3.2 3.4 3.6 4.0 5.0
100
50
20
40
ID/A
60
80
100
0
0
20
40
ID/A
60
80
100
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
RDS(ON)/mOhm
Fig.9. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V
a 2
6.5 6 5.5 5
30V TrenchMOS
1.5
1
4.5 4 3.5 3
0.5
3
4
5
6 VGS/V 7
8
9
10
0 -100
-50
0
50 Tj / C
100
150
200
Fig.7. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(VGS); conditions: ID = 25 A;
Fig.10. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 25 A; VGS = 5 V
August 1999
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
BUK9505-30A
2.5
VGS(TO) / V max.
BUK959-60
6 VGS/V 5
2 typ. 1.5 min. 1
2 3 4 VDS = 14V 24V
0.5
1
0 -100
-50
0
50 Tj / C
100
150
200
0
0
20
40
60
QG/nC
80
100
120
Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Sub-Threshold Conduction
Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS
100 ID/A 80
1E-01
1E-02 2% typ 98%
60 Tj/C = 40 175 25
1E-03
1E-04
20
1E-05
0
1E-05
0
0.1
0.2
0.3
0.4
0.5
0
0.5
1
1.5
2
2.5
3
0.6 0.7 VSDS/V
0.8
0.9
1
1.1
Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
20
Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120 110 100
15
90 80 70
Thousands pF
10
60 50 40
Ciss
5
30 20 10
0 0.01
0.1
1
VDS/V
10
Coss Crss 100
0 20 40 60 80 100 120 Tmb / C 140 160 180
Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A
August 1999
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
BUK9505-30A
+
L VDS VGS 0 RGS T.U.T. R 01 shunt
VDD
+
RD VDS
VDD
-ID/100
VGS 0 RG T.U.T.
-
Fig.17. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD )
Fig.18. Switching test circuit.
August 1999
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
BUK9505-30A
4,5 max 10,3 max
1,3
3,7 2,8
5,9 min
15,8 max
3,0 max not tinned
3,0
13,5 min
1,3 max 1 2 3 (2x)
2,54 2,54
0,9 max (3x)
0,6 2,4
Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK9505-30A
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
8
Rev 1.100

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